In the development of electronic products, due to the rapid evolution of semiconductor process technology, there have been powerful, complex large-scale integrated circuits. Some electronic products, such as mobile phones, tablet PCs, USB peripheral products, require single-chip applications; moreover, in the complex large-scale integrated circuit, the accurately synchronized clock signals are needed to achieve high-specification processing efficiency. Therefore, the clock generator, that is, the phase-locked loop (PLL), is widely used in the frequency synthesizer, clock and data recovery circuit, and so on.
For the known PLL, the reference frequency Fref inputted to the phase frequency detection (PFD) circuit is often generated by an external crystal oscillator or MEMS oscillator, which often results in increased power-consumption, and larger external PCB area and volume, presenting difficulty to product miniaturization and leading to increased cost.
For USB clock generator, a common structure used in USB system is to include a built-in oscillator in the chips in order to save a 12 MHz crystal oscillator, and the built-in oscillator is often an LC-tank (for low phase noise and low jitter), Ring oscillator, or RC-oscillator; however, the LC-tank type often increases device area size and power-consumption, and Ring oscillator or RC oscillator is unable to avoid phase noise and jitter, and unable to perform temperature compensation.
A general clock generator for USB system uses the USB start of frame (SOF) from the USB HOST for the digital PLL to lock the accurate frequency, and then uses the linear PLL (LPLL) to filter out the clock jitter generated by digital PLL. The major disadvantage is that the non-USB system does not have the SOF and is unable to provide the digital PLL for frequency locking and unable to obtain accurate frequency. Also, when the digital PLL performs frequency locking and calibration, a delay time for data reception will be increased, leading to practicality of the system.
In an article in IEEE Journal of Solid-State Circuits, March 2007, “A monolithic and self-referenced RF LC clock generator compliant with USB 2.0”, the author, Michael S McCorquodale, disclosed how to solve the problem of frequency change from the PLL caused by XTAL due to environmental change, such as, temperature. The solution is to add a phase interpolation circuit before feeding back to the frequency divider in the PLL to shift phase to achieve adjusting the PLL output frequency at different temperatures.
However, in the above document, the LC-tank oscillator increases the device area size and power-consumption, and the temperature compensation is done by capacitor array and switches (IPTAT+ICTAT); such an analog approach is prone to fabrication process drift. The calibration of center frequency uses binary weighting capacitor array and switches, leading to a rather large area; moreover, the output clock due to LC-tank high frequency needs high power-consumption current mode circuit for frequency division.
In the 26th International Conference on VLSI, January 2013, India, Abhirup Lahiri proposed a CMOS clock oscillator in the 30 MHz clock oscillator in 28 nm CMOS bulk process; however, the main disadvantage is that the lock signal frequency provided by the CMOS clock oscillator is a fixed frequency.
Taiwan Patent No. 1558095 titled “clock generation circuit and method” disclosed a clock generation circuit and a clock generation method to generate a clock. The clock generating circuit comprises: a reference clock generating circuit disposed in a chip for independently generating a reference clock; a temperature sensor for sensing ambient temperature to generate a temperature information; a temperature compensation module coupled to the temperature sensor for generating a temperature compensation coefficient based on the temperature information; and a clock adjusting circuit coupled to the reference clock generating circuit for generating the clock, based on the reference clock and the temperature compensation coefficient; wherein the temperature compensation module dynamically generates the temperature compensation coefficient so that the frequency of the clock approaches a target frequency and does not substantially vary with temperature. However, the temperature compensation module of the “Clock Generation Circuit and Method” of Taiwan Patent No. 1558095 generates the temperature compensation coefficient corresponding to each temperature based on the reference value and the slope, and the temperature compensation coefficient is obtained by interpolation of a value N.F for a certain temperature, in order to deduce backward to obtain the temperature compensation coefficient.
Taiwan Patent No. 1485986 “Clock signal synthesis method and apparatus” disclosed a method and apparatus of adjusting the frequency of the output clock signal to the required accuracy of the oscillation frequency. An embodiment of the method comprises the steps of: entering a calibration mode; generating a first control character to control the timing of a clock signal synthesizer; adjusting the first control character until the timing of the synthesizer is substantially within a preset range of a reference clock timing; sensing a temperature by using a temperature sensor; storing the output preset value of the first control character to a nonvolatile memory; exiting the calibration mode; using the temperature sensor to sense the temperature; and generating a second control character based on the output of the nonvolatile memory and the output of the temperature sensor to control the timing of the clock signal synthesizer. However, Taiwan Patent No. 1485986 “Clock signal synthesis method and apparatus” uses a single-point calibration and temperature compensation mechanism to maintain the frequency of the clock signal to within the accuracy range of the specified frequency under the influence of process, voltage and temperature fluctuation.
Therefore, the issues need to be addressed include how to include a built-in oscillator in the chip to replace the external crystal oscillator (XTAL) to achieve reducing data reception delay in data transmission, save system cost, adjust center frequency of the voltage controlled oscillator (VCO) digitally, and increase applicability to non-USB system without SOF.